The output

The generated HDL

What you carry away is ordinary RTL: one file per module, in the language you chose, written to be read by a person and consumed by the usual tools.

Where it lands

File	What it is
`2pyrtl_output/hdl/systemverilog/Module.sv`	The module, in SystemVerilog.
`2pyrtl_output/hdl/vhdl/Module.vhd`	The same module, in VHDL. Compile it as VHDL-2008.
`2pyrtl_output/hdl/vhdl/rtlpack_types_pkg.vhd`	VHDL only, when a module has an array or a width sized from a parameter: the types every array is declared with, one for each shape, and rtlpack_clog2, which sizes such widths.
`2pyrtl_output/rtl_arch/Module_PARAM_value_architecture.json`	The design itself - what the viewer draws from. One per set of parameter values; a long list of them is shortened, ending with a CRC.

A run rewrites these. Anything you want to keep, keep elsewhere - or take it with Download all, which hands you the whole workspace as a zip.

What it looks like

Parameters come out as parameters, your names stay your names, and the clock and reset are the ones your settings asked for. Nothing is flattened or renamed for the tool's convenience.

module Counter
   #(
      parameter WIDTH = 8
   )
   (
      input  clk,
      input  resetn,
      input  enable,
      output reg [WIDTH-1:0] count
   );


   always @(posedge clk or negedge resetn)
   begin
      if(resetn == 0) begin
         count <= 0;
      end
      else begin
         if(enable) begin
            count <= count + 1;
         end
      end
   end

endmodule

A design of several modules comes out as several files, each instantiating its children by name - the hierarchy you wrote is the hierarchy you get.

Taking it to your tools

·
Download the workspace, or copy the files you need out of 2pyrtl_output/hdl/.
·
For VHDL, analyse rtlpack_types_pkg.vhd before the modules that use it.
·
Write your own testbench, in your own simulator. 2pyrtl does not simulate - see below.

Partly checked against compilers

Our own tests run part of the generated HDL through real compilers - GHDL for VHDL, Verilator for SystemVerilog - and simulate some of it against testbenches. Not every construct is covered yet, Icarus is not part of the tests, and a few known cases still fail to compile. If your tool rejects something, that is worth telling us through the feedback button: it is exactly the kind of thing we want to hear about.

Choosing the language and the style

One setting picks SystemVerilog or VHDL; others decide the clock's name, whether reset is active low, whether it is synchronous, and how the output is indented. They live in src/ProjectConfig.py in your workspace, and every one of them is on the project settings page.