Introduction

What 2pyrtl is

2pyrtl is a web app where you describe your RTL (Register Transfer Level) description in Python using 2pyrtl’s built-in classes and its library of RTL modules (see rtlpack and rtllibpack respectively for the details), and as of now, generate two artifacts:

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  Synthesisable RTL files in SystemVerilog or VHDL that you can take to simulation and synthesis.
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  The schematic diagram, that you can rearrange as you prefer, and use it for your analyses or peer-reviews.

All the files you produce are yours. 2pyrtl’s library modules your design instantiates are covered by the Apache License 2.0, which lets you use them in your own work, freely including commercially, provided you keep their copyright notice and licence with what you distribute.

What 2pyrtl is not

As of now, 2pyrtl is not

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  an HDL simulator or
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  an HDL synthesis tool or
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  a place-and-route tool.

You need other tools available to you to simulate, synthesize or place-and-route the generated HDL files to the target ASIC standard-cell library or FPGA.

Why use 2pyrtl

Though 2pyrtl currently doesn’t support simulation, synthesis or place-and-routing, what it offers is:

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  Schematic diagrams for your RTL like the way a RTL designer actually expects. 2pyrtl’s schematics diagrams are generally far better for understanding and having deeper insights into the architecture than a standard-cell synthesized netlists visualized or schematics shown by most simulation tools. This is because synthesized netlists have too much details for humans to comprehend or need and the schematic diagrams shown by the simulation tools are generally uncustomizable, slow to load and in general not user-friendly to interact with.
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  Though 2pyrtl may not give timing or area information as accurately as a standard-cell or fpga synthesized netlist, it gives the feedback to the designer much faster (near instantly) and hence the write-analyse-fix loop is much faster. Also, you can analyse, the functionality as well as the timing* and area* in the same schematic rather than simulation tool showing the same RTL in almost unrecognisably different way than a synthesis and STA tools.
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  2pyrtl’s schematic is 100% accurate and 100% up-to-date by design. It is much easier and reliable to discuss, review or ramp up on other’s design if a bit-accurate schematic is available compared to discussing or reviewing either the HDL code or hand-drawn diagrams (which are almost never 100% accurate and never 100% up-to-date), or a combination of the two.
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  You don’t have to write RTL in SystemVerilog, Verilog or VHDL which are many a times too verbose and unautomated, especially VHDL. Needing you to write a lot of boiler plate code. With 2pyrtl, you can focus on the actual design, actual creativity than knowing the syntactical quirks of these languages. Also, because you write a python code, your RTL design and your automation scripts can be one, instead of in two separate worlds: 1. RTL files and 2. scripts.
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  Using functions in HDL languages may be modular but they are a nightmare during debug because many of the simulation tools can’t show what’s happening inside them. With the same modularity achieved through python, you get the best of both worlds where modularity of the code is maintained (logic written as python functions) but at the same time in the RTL, they turn into normal code as if a compiler performed function-inlining optimization, so no more debug nightmares.
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  It has many other features that enhance your overall user-experience designing RTL (as explained in the chapters ahead) and we are constantly adding more features that either automate boring stuff for you, or add better insights to your design, or improve the PPA (Performance, Power and Area) of your design, or remove any hurdle in specifying a tricky logic.

* timing and area information will be available in pro-tier accounts which is coming soon

How it works

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  Write your RTL code. In the editor window, you write your RTL code in Python using the classes defined in rtlpack (see rtlpack for more details) and following the conventions mentioned in the same page.
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  Run it. Hit Run button with your code file visible in the editor (The editor supports opening multiple files at a time in form of tabs. To select which file you want to run, you need to have the tab that belongs to the file selected i.e. your intended code is actually visible in the editor). All your files under src/ in your workspace are sent to a secure sandbox env where the selected file is executed; the file you run has to be under src/ too. The directory/file structure of src/ is recreated in the sandbox so the relative paths used inside your python code will work as if you are working on a local machine. The prints and errors from your code’s execution are streamed back to the console window, which help you analyse and fix your Python RTL description.
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  Visualize it. On a successful run, if the Follow runs button (the chain link on the viewer’s bar) is ON, the schematic will appear in the schematic viewer in a few seconds (depending on the complexity and size of your design). The corresponding architecture file(s) that the viewer uses to show the schematic is/are generated inside ./2pyrtl_output/rtl_arch directory as <Module instance type>_architecture.json (the module’s name followed by its parameters and their values; a long list of them is shortened, ending with a CRC, and the full values are in the file under ModuleParams). The schematic generated without any user input is auto-generated to the best of the tool’s ability and generally needs manual re-arrangement of components as you actually prefer. There are two ways to do this:

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    Using mouse in the schematic viewer to drag and place the components, wires, x/y-flip them and saving your changes. The re-arrangement done this way are saved in form of a json file called <Module instance type>.stf.json.
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    By defining logic to arrange the components as part _schematic() function inside your Python RTL file itself (See _schematic() for more details). The re-arrangement done this way is saved in form of <Module instance type>_architecture.json file itself.
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  Get HDL files for it. On a successful run, HDL file(s) are also generated inside ./2pyrtl_output/hdl/systemverilog or ./2pyrtl_output/hdl/vhdl directories depending on the settings you choose (See ProjectConfig.py for more details). You can download these HDL files (all of them, with the rest of your workspace, using the Download all button, or individually by opening a file in the editor and copying it) and use them for further analyses like simulation or synthesis.